The present invention relates to a semiconductor device and a test method for a semiconductor device, and relates, for example, to a technique for a semiconductor device on which a BIST (Built In Self Test) circuit is mounted.
Japanese Unexamined Patent Application Publication No. 2013-253840 discloses a method for realizing a BIST in a state where a semiconductor integrated circuit is mounted on a user system, using a BIST circuit which can be controlled with a JTAG interface in a semiconductor integrated circuit. Specifically, it includes a Power-On Self-Test circuit, a pattern generation circuit, a logic BIST circuit, and a memory BIST circuit. When a self-test execution signal is asserted, the Power-On Self-Test circuit selects an output of the pattern generation circuit in place of an external terminal group of a test access port, and supplies a test pattern generated by the pattern generation circuit to each BIST circuit.